"Logic Simulations System"

Supervised by G.Manson

Abstract

This project continues the work of Andrew Kinghorn, in producing a replacement for the PALASM software used to teach the basics of logical programming to undergraduate students. In the previous academic year a visual system was produced that could simulate logic circuits by connecting various components together. The addition of a Programmable Array Logic (PAL) chip allowed the user to enter logical programs in sum of product form.

The project had two main goals, the first being to produce a logical programming language similar in syntax to Java which could be used to produce a JEDEC file to program a PAL chip. The second goal was to integrate this into the visual system and to add extra functionality. A rapid iterative design methodology was used due to the sheer volume of work that needed to be completed to make the system usable. The visual system had many bugs, and this situation was not helped by the lack of documentation provided.

It was possible to create experiments to show the system worked and also that it could be used as a teaching tool. The minimisation of equations proved to be a complicated task and whilst the finalised minimiser works well, it does not always produce optimal results. Some features had to be omitted that would have been useful, in order that a complete integrated system could be delivered. Whilst the delivered system functions as intended it is clear that there is much room for future expansion and improvement of it.